1. Field of Invention
The present invention relates to an integrated circuit structure. More particularly, the present invention relates to an interconnect structure with an air gap.
2. Description of Related Art
Modern integrated circuits include devices such as field effect transistor (FETs) or bipolar devices formed in and on a semiconductor substrate in combination with a multilevel interconnect structure formed above and in contact with the devices. The multilevel interconnect structure provides connections to and between different ones of the devices formed in the substrate and so is an increasingly important aspect of aggressive designs for integrated circuits. In many integrated circuits, the multilevel interconnect structure includes one or more arrays of wiring lines extending in parallel to provide connections to and between the devices in closely packed arrays of devices. Such arrays of devices are typical of integrated circuit memories and other aggressive circuit designs. Closely spaced, parallel wiring lines can provide undesirable levels of capacitive and inductive coupling between adjacent wiring lines, particularly for higher data transmission rates through the arrays of parallel wiring lines. Such capacitive and inductive coupling slow data transmission rates and increase energy consumption in a manner that can limit the performance of the integrated circuits. For some aggressive circuit designs, the delays and energy consumption associated with the circuit""s interconnect structure are a significant limitation on the circuit""s performance.
The complexity of modem interconnect structures has become a major cost component for integrated circuit designs. Various factors threaten to further increase the proportional expense of the interconnect structure within integrated circuits. For example, proposals have been advanced for substituting different interlayer and inter-metal dielectric materials into multilevel interconnect structures to improve the coupling problem. The capacitive and inductive coupling between adjacent wiring lines is mediated by the dielectric material that separates the wiring lines. Present dielectric materials, such as silicon oxides deposited by chemical vapor deposition (CVD) from TEOS source gases, have comparatively high dielectric constant, and proposals have been made to replace these dielectric materials with dielectric materials having lower dielectric constant. Performance could be improved by replacing the higher dielectric constant materials with lower dielectric constant materials, with the theoretical minimum dielectric constant being provided by a gas or vacuum dielectric. Adoption of these alternate dielectric materials has not been completely satisfactory to this point in time, due to the increased cost and processing difficulty associated with these alternative materials.
One promising implementation of a multilevel interconnect structure using an air dielectric, that is, air gap is proposed. FIG. 1 is a cross-sectional view, schematically illustrating a typical interconnect structure with an air gap design. In FIG. 1, the substrate 10 has various devices (not shown). A dielectric layer 12 is formed over the substrate 10. First level wiring lines 20, 22 extend along the surface of the dielectric layer 12 and are separated by air gaps 32. The use of air gaps, as compared to more conventional dielectric materials, ensures that there is a minimal level of coupling between the adjacent first level wiring lines 20, 22. The first level air gaps are bounded on the bottom by the dielectric layer 12 and on the top by a thin layer of silicon oxide 30. Contacts to the first level wiring lines 20 include vertical interconnects 36 that extend from the first level wiring lines 22 to the second level wiring lines 46. The first level wiring lines 22 and the second level wiring lines 46 are connected by the vertical interconnects 36 in between, where the inter-metal dielectric layer 42 separates the first level wiring lines 22 and the second level wiring lines 46. These via level air gaps reduce the extent of capacitive and inductive coupling between the first level wiring level wiring lines 20, 22 and the second level wiring lines 46, as compared to more conventional solid dielectric materials. In a similar fashion, second level air gaps 52, bounded on top and bottom by thin layers of silicon oxide 49, 40, are provided between the second level wiring lines 46 to reduce the level of capacitive and inductive coupling between the second wiring lines. Air gaps 32, 52 surround the wiring lines 20, 22, 46.
In order to fabricate the structure as shown in FIG. 1, a sequence of processes in cross-sectional view is shown in FIGS. 2-5. In FIG. 2, a carbon layer 14 is formed on the dielectric layer 12. The carbon layer 14 is patterned by photolithography and etching process, so as to form openings 16 that expose the dielectric layer. The location of the openings 16 is the location where an wiring lines, such as the wiring lines 20, 22 of FIG. 1, is to be formed.
In FIG. 3, the openings 16 are filled with metal material by a typical damascene manner, so as to form the wiring lines 20, 22. The damascene manner typically includes depositing a blanket metal layer over the carbon layer 14, and polishing away the top portion of the metal layer. The residual metal layer fills the openings 16 to form the wiring lines 20, 22.
In FIG. 4, a thin silicon oxide layer 30 is formed to cover the carbon layer 14 and the wiring lines 20, 22. The substrate 10 with the carbon layer covered by the silicon oxide layer 30 is placed in a furnaces holding an oxygen ambient and heated to a temperature of 400xc2x0 C.-500xc2x0 C. for approximately two hours. In this environment, oxygen readily diffuses through the thin oxide layer 30 to react with the carbon layer 14, forming CO2 which diffuses back through the thin oxide layer and escapes. After two hours ashing period, the entire carbon layer 14 is consumed, leaving behind air gaps 32 between the oxide layer 30 and the dielectric layer 12 and separating the first level wiring lines 20, 22, as shown in FIG. 4. This process can then be repeated to produce the multilevel interconnect structure shown in FIG. 5, which is also the structure shown in FIG. 1. The via interconnects 36 in the inter-metal dielectric layer 42 is formed to connect to a next level interconnect 46 that are to be formed. The second level interconnect 46 is continuously formed by repeating similar process of depositing and patterning the carbon layer, and filling the interconnect 46. The silicon oxide layer 49 is formed covering the carbon layer 52 and the second level interconnect 46, such as the wiring lines. The carbon is evaporated away to leave the air gap 44.
In the conventional interconnect structure as shown in FIG. 1, the air gap is included. This can effectively reduce the capacitance of the interconnect dielectric layer. However, if a misalignment occurs during forming openings for the wiring lines, an unlanded via or wiring line would be formed. This is often when the device integration greatly increases. In this situation, the unlanded opening may also penetrate through the thin silicon oxide layers 30, 40, 49, and improperly expose the air gaps. When the material for via or wiring line to deposited into the unlanded opening, the material also enters the air gap, causing a failure of the device.
As embodied and broadly described herein, the invention provides an interconnect structure with air gap. A conductive structure, such as an unlanded via or a wiring line, can be formed without improperly penetrating into an undesired region of the interconnect structure.
The interconnect structure includes a substrate which has devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure enclosed by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening.
In the foregoing, if a multilevel interconnect structure is desired, multiple levels of air gap associating with multiple capping layers and etching stop layers can be repeatedly formed under the inter-metal dielectric layer.
A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.